/*
Tff_2 
	input clk,rst,
	input data,
	output q
	
	q<=data^q;
*/
`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
wire t1;
reg t1_r;
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		t1_r<=1'b0;
	end
	else begin
		t1_r<=data^t1_r;
	end
end
assign t1=t1_r;
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		q<=1'b0;
	end
	else begin
		q<=t1^q;
	end
end
//*************code***********//
endmodule